adder circuit
英 [ˈædə(r) ˈsɜːkɪt]
美 [ˈædər ˈsɜːrkɪt]
网络 加法电路
双语例句
- Design methods of one-bit full adder circuit
一位全加器实验电路设计方法的研究 - A Dynamic Full Adder Circuit Based on Single Electron Transistors
基于单电子晶体管的动态全加器电路设计 - A hexadecimal adder circuit example is introduced to describe how to apply VHDL to designing FPGA circuit based on Xilinx ISE. [ Ch, 16 ref.]
通过介绍一个16进制加法器的设计实现实例，描述了如何基于ISE平台使用VHDL语言进行FPGA电路设计的原理和方法。 - Alter the full adder cell from NMOS circuit to CMOS circuit. Basing on it, the paper introduces the design flow of converting NMOS circuit into CMOS circuit and some questions of the design.
将其中的全加器单元NMOS电路改为CMOS电路，本文以此为例，介绍了将NMOS电路改为CMOS电路时，建立CMOS单元库的流程及应注意的问题。 - This paper introduces a method using Multiplier and adder in order to replacing A/ D circuit in non-intermediate-frequency receiver.
本文介绍一种采用乘法器与加法器相结合电路替代一般零中频接收机中A/D转换电路的方法。 - This papers implements one bit adder based on Multiobjective Evolutionary Algorithm by using Handel-C. The result indicates that evolutionary design of circuit is implemented on the FPGA.
本文运用硬件描述语言Handel-C实现了基于多目标演化算法的一位全加器的电路设计，证明了在硬件上可实现电路的优化。 - The paper introduces a thermocouple temperature transmitter which uses linear amplifier, analog multiplier, adder and voltage/ current converter to achieve linear treatment. The linear treatment method and the relative circuit design theory are given.
介绍了一种利用线性放大器、模拟乘法器、加法器及电压/电流转换器实现线性化处理的热电偶温度变送器，给出了线性处理方法及相关的电路设计原理。 - A new pulse stream digital/ analogue based synapse multiplier/ adder can be realized. The synapse weight values don't need learning, and it can also lessen the complexity of circuit.
实现了一种脉冲流数字模拟混合突触乘法/加法器电路，而且该神经网络电路的突触权值不需要学习调整，降低了电路的复杂性。 - By the analyzing design of serial adder, this paper also describes in detail the design method of implementing the digital circuit with FPGA/ CPLD. The result of simulation and programmable down load devices using MAX+ PLUSII Design Compiler is successfully obtained.
以串行加法器的设计实例，系统地阐述了FPGA/CPLD实现数字电路的设计方法，并在MAX+PLUSII境下成功地进行了仿真和编程下载。 - Using Full Adder to Design Code Conversion Circuit Xiong
利用集成全加器设计码制转换电路 - The authors have succeeded in devising a1024bit circular adder and it has been used in the circuit of RSA cryptosystem with a good effect.
笔者现已成功地设计了1024位循环式加法器，并应用到RSA密码体系的硬件电路中，得到了较好的效果。 - The paper presents a multiplier circuit based on Booth algorithm when the radix equals four by studying the Booth algorithm. The carry-save-array adder and the pipeline technique are drawn into the design for improving the circuit speed.
通过对Booth算法的研究，本文提出了一种基4Booth算法的硬件乘法器电路，为了提高硬件乘法器电路的运算速度，将保留进位加法电路和流水线技术引入了该乘法器电路。 - The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。 - In contrast with the feed-forward modulator structures presented before, the adder is excluded from the proposed modulator. The circuit complexity and chip area are decreased.
与其它带前馈通道的调制器相比，本文提出的调制器结构不含加法器，有效地降低了电路的复杂度及芯片面积。 - After discussing the algorithm and the structure of prefix-carrying adder, we analyze the timing control technology of domino circuit deeply.
在研究了前置进位加法器的算法和结构基础上，又对多米诺电路的时钟控制技术进行深入的分析。 - Over the years, people put forward a number of rapid adder structure model, and Raised different types of circuit design to realize them.
多年以来，人们提出了许多快速加法器结构，并且以不同的电路设计类型加以实现。 - A 32-bit Sparse-tree adder is implemented with Full-custom way, the key techniques of the limited dynamic circuit design methodology are introduced, such as selection and design of dynamic circuits, noise immunity design and low-power design.
完成32位Sparse-tree加法器的定制设计，采用有限动态电路设计方法，并针对动态电路的选择与设计，抗噪声设计及低功耗设计进行了详细分析。 - First of all, a Z direction closed-loop control approach had been achieved in the AFM nano-machining system by using the adder circuit, through which the closed-loop control method and the open-loop control method can be switched.
首先实现了AFM纳米加工系统的Z向闭环加工方式，运用研制的加法器电路实现开环加工方式与闭环加工方式的切换。 - First, the static adder, transmision function adder and static Energy-Recovery full adder are realized in the subthreshold circuit.
首先，进行了静态加法器、传输功能加法器和静态能量恢复加法器的亚阈值电路实现。